module show(
			input fast_clock,
			input [15:0] data_in,
			output wire [4:0] cs_out, 
			output wire [6:0] dig);

reg [15:0] data;	
reg [2:0] cs_in;
reg [3:0] num_in = 0;
reg [31:0] num = 0;


always @(posedge slow_clock)
	begin
		data <= data_in;
		if(num==0)
			begin
				num <= num + 1;
				cs_in <= 0;
				num_in <= data % 10;
			end
		else if(num==1)
			begin
				num <= num + 1;
				cs_in <= 1;
				num_in <= (data / 10) % 10;
			end
		else if(num==2)
			begin
				num <= num + 1;
				cs_in <= 2;
				num_in <= (data / 100) % 10;
			end
		else if(num==3)
			begin
				num <= num + 1;
				cs_in <= 3;
				num_in <= (data / 1000) % 10;
			end
		else
			begin
				num <= 0;
				cs_in <= 4;
				num_in <= data / 10000;
			end
	end


div my_div(.fast_clock (fast_clock), .slow_clock (slow_clock));
choose my_choose(
				.cs_in(cs_in),
				.num_in(num_in),
				.cs_out(cs_out),
				.dig(dig));
endmodule 